Embodiments of the present inventive concepts relate to a non-volatile memory device, and more particularly, to a non-volatile memory device which may adjust frequency of a read operation or a program-verify operation in accordance with a noise level of a common source line, a method of operating the same and an electronic device having the same.
A semiconductor memory device is divided into a volatile memory device and a non-volatile memory device. The volatile memory device includes a dynamic random access memory (DRAM) and a static random access memory (SRAM), and the non-volatile memory device includes a flash memory, an electrically erasable programmable read-only memory (EEPROM) and a resistive memory.
The flash memory includes a memory cell array for storing data. The memory cell array includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells.
The plurality of memory cells are divided into an on-cell and an off-cell, respectively, according to distribution of a threshold voltage. The on-cell is an erased cell and the off-cell is a programmed cell.
A flash memory performs an erase operation on a memory block basis and performs a program operation or a read operation on a page basis.
A flash memory includes a cell string structure. A cell string includes a plurality of transistors connected in series between a string selection transistor connected to a string selection line (SSL) and a ground selection transistor connected to a ground selection line (GSL). The string selection transistor is connected to a bit line and the ground selection transistor is connected to a common source line (CSL).
Each of a plurality of memory cells may be embodied in a single level cell (SLC) for storing a bit or a multi-level cell (MLC) for storing a plurality of bits. The MLC has an erase state and a plurality of program states according to threshold voltages.
It is important that the MLC secures a margin of each of a plurality of program states by narrowing a distribution range of a threshold voltage in a program state. A noise of the CSL causes a distribution range of each of the plurality of program states to expand. The noise of the CSL means that a voltage of the CSL increases due to current flowing in an on-cell during a read operation or a program-verify operation. With an identical word line voltage or an identical bit line voltage, when a voltage level of a source node of a ground selection transistor increases due to a noise of the CSL, a current flowing in an on-cell decreases. This causes a threshold voltage of an on-cell to increase, so that an on-cell may be determined as an off-cell and cause an error during a read operation or a program-verify operation.